So let's say I wanted to design an imageboard server on an FPGA.
No general-purpose computing or higher-order logic, it's not meant to be Turing-complete. I want the thing to natively speak chan at an electronic level.
It'd be broken down into a number of functional blocks and subunits, first of all.
One communications subunit for Ethernet PHY, MAC, TCP, and IP.
One data subunit for storage and retrieval of bulk data, and intrinsic microcode to handle that.
One control subunit, which contains registers/counters, and processes and fetches instructions from storage, starting at the microcode.
And one subunit containing necessary electronics like power-distribution, clocks, etc.
The core of the system would be a simple instruction fetch in the control subunit, which runs a small microcode from storage to prepare configuration and state.
Storage would be handled by an MMC or NAND driver, and said storage holds the higher-level code implementing the imageboard: a table of jmps correlating addresses to post IDs, and a post structure of simple "fetch [range]; jmp [template code subroutine]; fetch [range]" and so forth.
A couple registers will contain the current post ID, and the IP session of whoever's being served at that moment.
I fear the hardest part, would be keeping all the multiple internet sessions open, alive, and having data clocked out to them/in from them appropriately.