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File: e32efeb5feb31c6⋯.jpg (708.06 KB, 1920x1080, 16:9, RVPC_Finished.jpg)


>While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, for e.g. IoT and edge processing — one question that people cannot help but ask is, so when can I have a RISC-V PC? The answer to which is, right now.


Only 4000$ !


I saw the FPGA and was worried that the RISC-V was actually implemented on it. Apparently the FPGA is used to provide some kind of bus for the user to create his / her own USB and PCIe connections. That's kind of a bust for me if there isn't USB. It says PCIe is already implemented with 3 slots, 1 being M.2 but I only glanced over the webpage.


Why is a $2k FPGA needed for USB and PCI? Have I been in a coma? Did the world stop making phy controllers?



Propietary botnet. Leave.



>custom silicon for accelerating specific tasks

Okay it's CISC bloat.

What other free hardware cpu arch is out there?


Can someone explain the advantages and disadvantages of various architectures? Like when would you be better off using MIPS, POWER, RISC-V, etc.?

From what I have heard it seems like you use SPARC or POWER when you need lots of floating point calculations. MIPS and ARM for low electrical usage. And x86 for everything at a monetary cost. RISC-V's benefits seem to be the fact that it's open and free.

Is that right? Can people expand on this to talk about specific cases in either hardware or software projects where you'd pick 1 over the other and why.



arent these all the same thing but programmed differently



RISC-V is two things:

1) An academic project from some guys who, not content to merely accept public funding and hold highly coveted tenured jobs, have also decided that they need to (try to) get rich off of the tech they built with public funding

2) An effort to dislodge ARM and to a lesser degree MIPS in the SoC market

Thus this financial albatross of a "PC" is really just a mobile phone without mobile phone capabilities. Also there's no such thing as "open" silicon since you cannot inspect silicon nondestructively.

So how do they plan to compete with ARM and MIPS? Basically MIPS is dead and ARM is super expensive to license. So their plan is to ignore MIPS and try to undercut ARM's licensing and dev costs.

Are they innovating in performance/watt/dollar? No. It's just another low-end SoC.

Is the ISA open? Yes but who gives a fuck. Anyone who's ever worked with MIPS knows how extensible ISAs inevitably wind up: tons of shit that's supposedly compatible, but due to proprietary instruction-set extensions, none of it is actually compatible at all.


File: 9b701d32ef804e9⋯.jpg (31.82 KB, 670x377, 670:377, zeebo.jpg)


>a mobile phone without mobile phone capabilities.



>rsic-v pc

>can't do anything




having more instructions makes programming easier and technically should make it faster although this is diminishing gains. Also the instruction set decides how big or small your code is going to be aka how many bits your instructions can be stored in. More instructions set more momory is required



Couldn't an FPGA be used instead of a regular CPU so that one uses a custom set of instructions? Having a customizable architecture sounds more like what a regular freetard would want his computer to behave like.

I barely know anything about the topic so pls no bully



>having more instructions makes programming easier

It's true if you're talking about something bare like Alpha, but not something as bloated as amd64 or vax.

>and technically should make it faster although this is diminishing gains.

This is a known hoax. See https://people.eecs.berkeley.edu/~krste/papers/EECS-2016-130.pdf (The Renewed Case for the Reduced Instruction Set Computer:

Avoiding ISA Bloat with Macro-Op Fusion for RISC-V) and http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf (Code Density Concerns for New Architectures).


>>1029868 RISC-V is in its initial stage so its price is high. But later many companies adopt it as their architect, its price may drop sharply.



The instruction set is customizable at design time, but is set in stone when the SoC goes to the fab.

This is a common thing for SoC cores: you have a CPU of some kind together with an on-die bus. This bus can then link your CPU to other specialized logic.

Examples: think about various application-specific coprocessors: things for audio processing, crypto, compression.

You can do this stuff in software on your CPU, but if low-power is a goal for your device, having specialized silicon can save a lot for some tasks.

For CPU cores designed with this use case in mind, the bus will be part of the ISA specification, and will typically be engineered around the CPU's pipeline with the goal of saving power and avoiding pipeline stalls. It's also usually optimized to be easy to engineer with and to occupy very little space on the chip.

RISC-V did not invent this approach. Variants on this the idea were behind MIPS early rise to success and eventually was adopted by ARM through various kludges. You can also find this approach in other open-source SoC projects such as OpenSoC.



For whatever reason the geniuses decided to provide USB support via soft core. The majority of the cost in the SiFive PC setup is for the MicroSemi FPGA board needed to support this.

Competent silicon engineers would have used off the shelf silicon instead but that wouldn't help MicroSemi's over-priced under-performing shit look relevant so there you have it.


You could soon be designing your own RISC-V CPU..

I must say I really enjoy reading this ongoing blog series on designing a CPU on FPGA. In the latest posts he has made his Terrible Processing Unit (TPU) into an RPU with an RV32I ISA decoder.





Can be scalable, doesn't have those pesky EOL support.


RISC lets the freetard create better hardware acceleration or some hardware optimization. It's only a matter of good code which brings back the good old assembly programming days and it's definitely worth a shot to learn it on RISC rather than some proprietary i9 or ryzen botnet that's over complicated and either has some malicious hidden instruction to broadcast file hash and strings over its very own dedicated 3G botnet or some entropy backdoor.



>SiFive Freedom U540 SoC


Thank you, but I am not interested.


Open source is always right and it is justice! So RISC-V is superior!


File: 4128194550c31e9⋯.jpg (676.85 KB, 3000x1500, 2:1, elon-wtf.jpg)

all of the RISC machines in the 80's and 90's and even early 2000s, like SUNs and SGI workstations, ALL were overpriced BUT packed in a beautiful case.

this thing looks like shit.

You want to sell RISC archi? Pack it on a Micro-ATX or ITX format.



Can't have your machine botnetted if it has no capabilities.


I feel like bigsilicon taking this and making it their bitch kind of defeats the whole purpose of it being an "open" platform.



But can it run Crysis?



That IS the entire purpose. If it all were under one standard, and with guaranteed freedom, not a single company would so much as take a glance at it.


File: 6d2eca868c93d5f⋯.jpg (88.24 KB, 640x480, 4:3, 3drunkfarksysadmin.jpg)

Western Digital just released their RISC-V SweRV cores





If one company takes it and does impressive but closed things with is, how transferable is that progress to a open ethical company?



Impossible to transfer.


As someone who actually does HDL for a job these threads always make me chuckle.


>The instruction set is customizable at design time

This is not an attractive thing to any 3rd party with an ounce of common sense.


<decide to have a quick look through it

>looks to be a bog standard minimal RISC-V core

>all the storage acceleration is clearly done on dedicated hardware that isn't included in the repo

>said hardware looks to be as old as the late 90s given that they have a AHB to AXI4 converter

>what is released is all in RTL, which has comments

Since you don't seem to understand what you are looking at let me spell it out for you: this is WD trolling you claiming this is open source is like saying that Fortnite is open source because you are free to look at the assembly for the Epic Games launcher. This is just the core which runs a few thousand lines of C firmware while all the actual processing is done by dedicated hardware which remains closed source.



lol, you're not very good at your job are you?


Can someone compare it's theoretical performance to Power and Russian Elbrus?

To me it only seems like a ARM replacement and ARM isn't very suited for heavy computation.


>>1031072 It is enough if it has similar performance to ARM CPUs'. Because it is an open source architecture so its performance is not important. Some companies may use it because its blueprints are open and free.



I think I remember seeing some papers claiming it'd beat ARMv7 on the speed:power usage:area stage.



>performance is not important



>not important

Wew, we're reaching /g/ levels here.

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