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File: e32efeb5feb31c6⋯.jpg (708.06 KB, 1920x1080, 16:9, RVPC_Finished.jpg)


>While it’s clear that the most significant opportunities for RISC-V will be in democratising custom silicon for accelerating specific tasks and enabling new applications — and it’s already driving a renaissance in novel computer architectures, for e.g. IoT and edge processing — one question that people cannot help but ask is, so when can I have a RISC-V PC? The answer to which is, right now.


Only 4000$ !


I saw the FPGA and was worried that the RISC-V was actually implemented on it. Apparently the FPGA is used to provide some kind of bus for the user to create his / her own USB and PCIe connections. That's kind of a bust for me if there isn't USB. It says PCIe is already implemented with 3 slots, 1 being M.2 but I only glanced over the webpage.


Why is a $2k FPGA needed for USB and PCI? Have I been in a coma? Did the world stop making phy controllers?



Propietary botnet. Leave.



>custom silicon for accelerating specific tasks

Okay it's CISC bloat.

What other free hardware cpu arch is out there?


Can someone explain the advantages and disadvantages of various architectures? Like when would you be better off using MIPS, POWER, RISC-V, etc.?

From what I have heard it seems like you use SPARC or POWER when you need lots of floating point calculations. MIPS and ARM for low electrical usage. And x86 for everything at a monetary cost. RISC-V's benefits seem to be the fact that it's open and free.

Is that right? Can people expand on this to talk about specific cases in either hardware or software projects where you'd pick 1 over the other and why.



arent these all the same thing but programmed differently



RISC-V is two things:

1) An academic project from some guys who, not content to merely accept public funding and hold highly coveted tenured jobs, have also decided that they need to (try to) get rich off of the tech they built with public funding

2) An effort to dislodge ARM and to a lesser degree MIPS in the SoC market

Thus this financial albatross of a "PC" is really just a mobile phone without mobile phone capabilities. Also there's no such thing as "open" silicon since you cannot inspect silicon nondestructively.

So how do they plan to compete with ARM and MIPS? Basically MIPS is dead and ARM is super expensive to license. So their plan is to ignore MIPS and try to undercut ARM's licensing and dev costs.

Are they innovating in performance/watt/dollar? No. It's just another low-end SoC.

Is the ISA open? Yes but who gives a fuck. Anyone who's ever worked with MIPS knows how extensible ISAs inevitably wind up: tons of shit that's supposedly compatible, but due to proprietary instruction-set extensions, none of it is actually compatible at all.


File: 9b701d32ef804e9⋯.jpg (31.82 KB, 670x377, 670:377, zeebo.jpg)


>a mobile phone without mobile phone capabilities.



>rsic-v pc

>can't do anything




having more instructions makes programming easier and technically should make it faster although this is diminishing gains. Also the instruction set decides how big or small your code is going to be aka how many bits your instructions can be stored in. More instructions set more momory is required



Couldn't an FPGA be used instead of a regular CPU so that one uses a custom set of instructions? Having a customizable architecture sounds more like what a regular freetard would want his computer to behave like.

I barely know anything about the topic so pls no bully



>having more instructions makes programming easier

It's true if you're talking about something bare like Alpha, but not something as bloated as amd64 or vax.

>and technically should make it faster although this is diminishing gains.

This is a known hoax. See https://people.eecs.berkeley.edu/~krste/papers/EECS-2016-130.pdf (The Renewed Case for the Reduced Instruction Set Computer:

Avoiding ISA Bloat with Macro-Op Fusion for RISC-V) and http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf (Code Density Concerns for New Architectures).


>>1029868 RISC-V is in its initial stage so its price is high. But later many companies adopt it as their architect, its price may drop sharply.



The instruction set is customizable at design time, but is set in stone when the SoC goes to the fab.

This is a common thing for SoC cores: you have a CPU of some kind together with an on-die bus. This bus can then link your CPU to other specialized logic.

Examples: think about various application-specific coprocessors: things for audio processing, crypto, compression.

You can do this stuff in software on your CPU, but if low-power is a goal for your device, having specialized silicon can save a lot for some tasks.

For CPU cores designed with this use case in mind, the bus will be part of the ISA specification, and will typically be engineered around the CPU's pipeline with the goal of saving power and avoiding pipeline stalls. It's also usually optimized to be easy to engineer with and to occupy very little space on the chip.

RISC-V did not invent this approach. Variants on this the idea were behind MIPS early rise to success and eventually was adopted by ARM through various kludges. You can also find this approach in other open-source SoC projects such as OpenSoC.



For whatever reason the geniuses decided to provide USB support via soft core. The majority of the cost in the SiFive PC setup is for the MicroSemi FPGA board needed to support this.

Competent silicon engineers would have used off the shelf silicon instead but that wouldn't help MicroSemi's over-priced under-performing shit look relevant so there you have it.


You could soon be designing your own RISC-V CPU..

I must say I really enjoy reading this ongoing blog series on designing a CPU on FPGA. In the latest posts he has made his Terrible Processing Unit (TPU) into an RPU with an RV32I ISA decoder.





Can be scalable, doesn't have those pesky EOL support.


RISC lets the freetard create better hardware acceleration or some hardware optimization. It's only a matter of good code which brings back the good old assembly programming days and it's definitely worth a shot to learn it on RISC rather than some proprietary i9 or ryzen botnet that's over complicated and either has some malicious hidden instruction to broadcast file hash and strings over its very own dedicated 3G botnet or some entropy backdoor.



>SiFive Freedom U540 SoC


Thank you, but I am not interested.


Open source is always right and it is justice! So RISC-V is superior!


File: 4128194550c31e9⋯.jpg (676.85 KB, 3000x1500, 2:1, elon-wtf.jpg)

all of the RISC machines in the 80's and 90's and even early 2000s, like SUNs and SGI workstations, ALL were overpriced BUT packed in a beautiful case.

this thing looks like shit.

You want to sell RISC archi? Pack it on a Micro-ATX or ITX format.



Can't have your machine botnetted if it has no capabilities.


I feel like bigsilicon taking this and making it their bitch kind of defeats the whole purpose of it being an "open" platform.



But can it run Crysis?



That IS the entire purpose. If it all were under one standard, and with guaranteed freedom, not a single company would so much as take a glance at it.


File: 6d2eca868c93d5f⋯.jpg (88.24 KB, 640x480, 4:3, 3drunkfarksysadmin.jpg)

Western Digital just released their RISC-V SweRV cores





If one company takes it and does impressive but closed things with is, how transferable is that progress to a open ethical company?



Impossible to transfer.


As someone who actually does HDL for a job these threads always make me chuckle.


>The instruction set is customizable at design time

This is not an attractive thing to any 3rd party with an ounce of common sense.


<decide to have a quick look through it

>looks to be a bog standard minimal RISC-V core

>all the storage acceleration is clearly done on dedicated hardware that isn't included in the repo

>said hardware looks to be as old as the late 90s given that they have a AHB to AXI4 converter

>what is released is all in RTL, which has comments

Since you don't seem to understand what you are looking at let me spell it out for you: this is WD trolling you claiming this is open source is like saying that Fortnite is open source because you are free to look at the assembly for the Epic Games launcher. This is just the core which runs a few thousand lines of C firmware while all the actual processing is done by dedicated hardware which remains closed source.



lol, you're not very good at your job are you?


Can someone compare it's theoretical performance to Power and Russian Elbrus?

To me it only seems like a ARM replacement and ARM isn't very suited for heavy computation.


>>1031072 It is enough if it has similar performance to ARM CPUs'. Because it is an open source architecture so its performance is not important. Some companies may use it because its blueprints are open and free.



I think I remember seeing some papers claiming it'd beat ARMv7 on the speed:power usage:area stage.



>performance is not important



>not important

Wew, we're reaching /g/ levels here.



so it's usb 4 and 5 proof



Your an idiot, and there is so much FUD in your answer its crazy.

>not content to merely accept public funding and hold highly coveted tenured jobs, have also decided that they need to (try to) get rich off of the tech they built with public funding

wtf are you talking about? There is nothing abnormal about a professors research being funded by DARPA, or a professor founding a company based on that research - However, what company are you accusing Patterson of having built? RISC-V is a non-profit foundation. Patterson is retired, was an engineer at Google, has won countless awards, and has written THE canonical book in microprocessor design. He also powerlifts competitively and wins. He is based. What wrong doing are you actually accusing him of?

> Also there's no such thing as "open" silicon since you cannot inspect silicon nondestructively.

There is no such thing as open source C code, because you can't inspect compiled C code. The design being open source isn't the same as the product being inspectable - your retarded. Also, if you knew absolutely anything about RISC-V you know that its an open ISA, not microarichtecture, or hardware design. LowRISC is another university project to produce an Open Source Hardware implemntation of the RISC-V ISA, but RISC-V itself isn't open hardware because it isn't hardware.

>really just a mobile phone without mobile phone capabilities.

Nigga, who gives a fuck. Some people want open computers they control even without a touch screen. Servers are a thing.

>So their plan is to ignore MIPS and try to undercut ARM's licensing and dev costs. Are they innovating in performance/watt/dollar? No. It's just another low-end SoC.

Absolutely retarded. RISC-V is just an ISA. Its not an implementation. No performance specifications can exist for an ISA. RISC-V is a project to produce an OPEN ISA that many vendors can use without paying a licensing fee. Because instruction encoding is fixed, it means binary compatibility between processors across companies. This will produce a competitive, consumer friendly market while reducing licensing fees for companies producing microprocessors. An Open ISA makes sense.

As to why SOC's are being produced instead of desktop systems is clear. Spending billions of man hours engineering a desktop processor to compete with intel is a horrible idea. First, you wouldn't have a whole system - you would need to engineer a motherboard, which is also expensive and time consuming. Second, no desktop software currently runs on RISC-V ISA. Its unlikely that Microsoft or Apple would port their respective operating systems, or ISVs would port their software. It would be a huge waste of time and money. The embeded and cellphone market, however, is way different. They are incredibly price sensative to CPU's, and the engineering is simpler. They are also the fastest growing market segments.

If you want a RISC-V processor with intel like performance, nothing fundamental prevents that except your lack of billions of man hours to spend and expertise. Let the market develop instead of bitching about whats available.


RISC will never gain any serious traction. It's a stillbirth.



you can inspect compiled C code, and you must in order to find GPL violations



absolutely retarded. RISC is the only thing with traction. Every single processor since the late 90s has been RISC. CISC processors now convert to RISC for internal pipelines.



>Every single processor since the late 90s has been RISC

except the most popular ones that people actually use for desktops and servers.

>CISC processors now convert to RISC for internal pipelines.

Stop with this meme. It's like a fat fuck being like "I'm skinny on the inside!!"


File: efb632e0665915f⋯.jpg (90.94 KB, 403x403, 1:1, 1462484310116-0.jpg)


>a renaissance in novel computer architectures

Yeah novel architectures where you have to reimplement fucking overflow checks yourself. Who needs correct arithmetic when you can --omg-optimize?


The problem with RISC-V is that it's RISC. RISCs suck because they push the work onto compilers, which decades of experience shows is not as good as hardware. That's why the Itanium sucked even though it was technically faster than x86. Compilers just couldn't make use of it even though they're extremely bloated. There are other examples like IBM's Cell and all the SIMD crap in x86 that show that magic bloated compilers don't work and lead to slower code. Another problem with RISC is that simple tasks become complicated and need a ton of code instead of letting the hardware do it. Even simple x86 instructions like 32-bit integer ADD can turn into 6 or more on a RISC.

This was written in 1982 about the Burroughs 5000 from the early 60s. Descendants of this machine are still being made today by Unisys. Just like UNIX and Plan 9, RISC "research" is worse than what was around in the 60s. There's nothing "academic" about it.


In the desktop world, there were Symbolics Lisp machines and Xerox workstations.


If you read the RISC-V propaganda, they tell you that they are designing a computer that requires GCC and Linux or some equally bloated UNIX bullshit. Making a better platform is not one of their goals. Why didn't they try inventing a free CPU architecture that was good?

    "RISC is to hardware what the UNIX operating system
[sic] is to software."

Subject: Wait, I thought RISC was a *good* idea

No, the quote is exactly right. RISC is a lazy solution
along the lines of "well, we don't know how to write
compilers that use complex instructions efficiently, and we
don't know how to design complex hardware that runs fast, so
we'll make everything simple, and we can advertise we run at
80Mhz even though the system supports fewer user than a 1
MIP DEC-20."

It's exactly analagous to "you can use pipes and
redirection shell scripts to do anything, so we don't have
to write any REAL programs" and "portability is more
important that usability" philosophies so rampant in the
unix world.

(Was I properly vitrolic this time?)



>Only 4000$ !

And you had me going OP.




It's not as free as you think. Read what Luke - the creator of Libre Risc-V says about it:


>What’s particularly challenging is that I am neither permitted to report bugs (because they use GitHub) nor join the RISC-V Foundation due to clear cognitive dissonance and ethical conflict of interest in Sections 1.9 and Section 5 of the RISC-V Member Charter Agreement. Not only that, but other people on the “outside” - those who have spent considerable time helping to make RISC-V better - have been shut out due, for example, to a corporation pulling out of the RISC-V Foundation, their employee being the chair of one of the working groups, and the entire working group was shut down. The control exerted by corporate interests has therefore not gone unnoticed.


<> > there *is* no room for Libre *COMMERCIAL* products to interact with

<> > RISC-V Foundation members because all RISC-V Foundation members are

<> > forced to sign an agreement (for cross-licensing and patent protection

<> > purposes).

<> >

<> > this is clearly violating FRAND terms of Trademark Law, by being

<> > "Discriminatory" against Libre Commercial products.

<> >

<> > it is quite clear that the RISC-V Founders never envisaged a scenario

<> > where Libre *COMMERCIAL* products would ever be successful.


<> What? Why no interaction?

>because whilst most libre hardware engineers have entirely given up

>hope of being a welcome part of the RISC-V Community, i've been

>persistently reminding them that ITU-style secretive closed-doors

>development practices are effectively a cartel.

>this pissed them off, despite the fact that people have been talking

>*privately* about the exact things which i made public, for many

>years, long before i started.



>Computer Architecture: A Quantitative Approach

>The Canonical Textbook on Microprocessor Design

>Chapter 1

>The RISC-based machines focused the attention of designers on two critical performance techniques, the exploitation of instruction-level parallelism (initially through pipelining and later through multiple instruction issue) and the use of caches (initially in simple forms and later using more sophisticated organizations and optimizations). The RISC-based computers raised the performance bar, forcing prior architectures to keep up or disappear. The Digital Equipment Vax could not, and so it was replaced by a RISC architecture. Intel rose to the challenge, primarily by translating 80x86 instructions into RISC-like instructions internally, allowing it to adopt many of the innovations first pioneered in the RISC designs. As transistor counts soared in the late 1990s, the hardware overhead of translating the more complex x 86 architecture became negligible. In low end applications, such as cell phones, the cost in power and silicon area of the x 86-translation overhead helped lead to a RISC architecture, ARM, becoming dominant.

If you would stop being a double nigger and actually read a goddamn book on the shit you talk about, maybe you would understand.



>Price-performance ratio matters!


File: 4c7b595ae57445f⋯.jpg (43.64 KB, 637x622, 637:622, pepe.jpg)


$4k is lot of shekels for a quad core system. I think I will wait for the DVD so to speak.



An FPGA PC would let you customize and replace the instructions and entire architecture. You can build a really novel architecture like a Lisp machine, Haskell Reduceron, or massively parallel neural network, as well as simulate any computer with fewer than a certain number of transistors.



What I am very curious to know is how powerful and expensive of an FPGA would one need to buy to be somewhat on par with performance of an ARM SBC (or any decent daily driver). I've been contemplating this for a while but I haven't invested the time nor have I done enough research to determine what hardware would fulfill this requirement.




>64-bit quad-core RISC-V processor built in TSMC 28nm process, plus 8GB DDR4

>4000 dollarydoos

Nigga is this 1989? I can't pay that much for whats basically a nuc



>The control exerted by corporate interests has therefore not gone unnoticed.

Great, yet another foss/fosh project cucked by corporations, how long until the harassment accusations begin? any pink-haired cunts in the project?



Are you baiting or just stupid?



>4 month of yangbucks

imma pass



>Great, yet another foss/fosh project cucked by corporations, how long until the harassment accusations begin? any pink-haired cunts in the project?

Don't worry, Luke found a way around it. He is creating libre processor and GPU/VPU without help of Risc-V Foundation. Tbh he could just stop using Risc-V trademark and fork the ISA.



Hate to break it to you but that's bullshit. Current x86 is just:

>komplex instructions in

>get turned into lots of microps

>microops get processed

You'd be saving a step if you put in simple instructions.

>Compilers just couldn't make use

GCC is fine. The reason we don't have ARM PCs is because those fuckers only care about the mobile market and have no UEFI/BIOS standardization, so you'd have to make an individual OS for every fucking ARM SoC.



>make an individual OS for every fucking ARM SoC

Not really, it's more of a distro for each tpye of ARM chip not each SoC, and even then it's just using a different toolchain at compile time. The rest is up to the HW manufactures releasing proper DTB and DTS files for defining the I/O because there is no BIOS/UEFI so the system doesn't know where I/O or RAM is at boot up.



if it wasnt 4000 dolla i would buy



It's not really meant for desktop use right now, more that it's used for validating the ISA for emulators and simulators. FPGAs are a better option for this right now if you just want a secure RISC-V proc. If you want a pure RISC desktop IBM POWER is a better option right now. POWER has a lot more support from the Linux Kernel as well.



100% correct.

>You'd be saving a step if you put in simple instructions.

Word for Word what Patterson says in the cannonical text:

> In low end applications, such as cell phones, the cost in power and silicon area of the x 86-translation overhead helped lead to a RISC architecture, ARM, becoming dominant.


Stay Mad.

x86 is a RICS processor with an translation layer around the outside. CISC adopted a RISC design internally, and all successful processors since the 90s have.










K, your competition to beat is IBM Power (fully open source chip init+firmware) and OpenSPARC (fully open source design).

Is this actually any better than those two?



>About a year ago, I had a heated debate with a SiFive founder about how open they can get about their documentation.


>However, even one of their most ardent open-source advocates pushed back quite hard when I suggested they should share their pre-boot code.


> I’m talking about the code that gets run before the architecturally guaranteed “reset vector”. A number of software developers (and alarmingly, some security experts) believe that the life of a CPU begins at the reset vector. In fact, there’s often a significant body of code that gets executed on a CPU to set things up to meet the architectural guarantees of a hard reset – bringing all the registers to their reset state, tuning clock generators, gating peripherals, and so forth. Critically, chip makers heavily rely upon this pre-boot code to also patch all kinds of embarrassing silicon bugs, and to enforce binning rules.

If SiFive was unwilling to share the code for this, how open is their hardware really?


As a reminder, RISC-V is mainly gaining interest because it lets vendors create custom+proprietary chips based around a BSD licensed core that they don't have to pay licensing for (unlike ARM).

This is why you see corps like WD taking an interest, because they can stop paying ARM for the controllers in their hard drives, etc.

4000 USD

At this price there really is no point, especially when an OpenPOWER Blackbird board+CPU+cooler will give you 32 threads and PCIe 4 for 1600 USD.




No, you would disasemble it and look at the assembly code; not try to inspect a raw binary.



That... kinda makes some sense




I love Donald Trump! Heil Israel MIGA 2020!!!


This is a slide thread. SAGE AND REPORT


Yeah, fuck off boomer. Nobody cares.

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